1. Field of the Invention
This invention relates to the field of integrated circuits and, more particularly, to design methodologies for integrated circuits.
2. Description of the Relevant Art
Integrated circuits are employed in many different products. Generally, an integrated circuit includes a relatively large number of transistors (perhaps 1 to 5 million in modern integrated circuits, for example) formed upon a semiconductor substrate. The transistors are connected together using two or more wiring layers placed above the transistors, separated from the transistors and other wiring layers with an appropriate dielectric material.
Given the relatively large number of transistors included upon an integrated circuit, it is not feasible to design each transistor and its interconnection to other transistors. Instead, integrated circuit designers typically specify the operation of the integrated circuit using a high level design language (HDL) such as Verilog or VHDL. The description of the integrated circuit is typically a register-transfer level (RTL) description. An RTL description comprises multiple storage devices (e.g. the "registers") which store a current state of the integrated circuit, and a set of logical equations defining a next state of the integrated circuit. The next state is stored in the storage devices according to a clock signal defined for the integrated circuit. The clock signal defines the interval of time in which the next state is to be computed, and is used by the storage devices to determine when to sample an input to the storage device. The input thus sampled is stored in the storage device until the subsequent sampling point occurs upon the clock signal. For example, the rising or falling edge of the clock signal may be used as a sampling point. Alternatively, a storage device may "open" (i.e. allow the input to pass through to the output) during one phase of the clock signal (e.g. logical high or logical low value), and "close" (i.e. store the value upon the input regardless of subsequent changes upon the input) during the other phase of the clock signal. One period of the clock signal is referred to as a clock cycle.
HDLs can be used to provide a readily understandable description of the operation of an integrated circuit. The RTL description may be read by a person unfamiliar with the integrated circuit's operation, and the person may come to an understanding of the operation more quickly than if the person studied the transistors which implement the integrated circuit. However, RTL descriptions must be compiled into a list of transistors and their relative placement upon the semiconductor substrate, as well as a description of the wiring layers used to interconnect the transistors, in order to actually manufacture the integrated circuit. Typically, the integrated circuit design is divided into multiple partitions. At least one RTL description file is associated with each partition.
The process of compiling an RTL description includes a first compiling step, referred to as synthesis, which converts the RTL description into a list of cells and interconnection there between. The list of cells interconnected as specified by the synthesis tool implements the logical next state equations of the RTL description, as well as the storage devices in the RTL description. The cells available to the synthesis tool are provided to the synthesis tool in the form of a cell library comprising multiple cells. Each cell has a set of attributes defining the cell's logical, electrical, and physical properties. One cell attribute is a logical function (such as AND, OR, NAND, NOR, etc., or a complex logical function implementing an equation of basic logical functions) between one or more input pins and one or more output pins of the cell. A second cell attribute is timing information regarding the delay between a signal arriving at a particular input to the cell and an output signal from the cell reacting to the input signal. Each cell is associated with a corresponding circuit including a set of transistors arranged for placement upon an integrated circuit and interconnect between the transistors. The area occupied by the corresponding circuit is a third cell attribute included in the cell library. Furthermore, the timing information referred to above is derived from the circuit and from parameters defined for the semiconductor fabrication process in which the circuit is to be implemented.
The synthesis tool uses the logical functions of the cells in the library to realize the logical next state equations defined in the RTL description. Additionally provided to the synthesis tool is a set of constraints for the design, including a maximum desired clock cycle time and maximum area for the integrated circuit (or portion thereof, in the case of a partitioned integrated circuit). The synthesis tool attempts to realize the RTL description using the cell library within the clock cycle time and area constraints, as well as any other constraints provided to the synthesis tool.
The RTL description of the integrated circuit is typically synthesized multiple times during the design of the integrated circuit. The early synthesis results tend to include a number of logic paths (i.e. interconnected levels of cells between two storage devices) which do not meet the design constraints. Integrated circuit designers analyze the results of the earlier synthesis runs and change the integrated circuit design and/or optimize the RTL description to improve the results of later synthesis runs. Once a design has substantially achieved the design constraints, a second compiling step is performed. The lists of cells corresponding to each partition of the integrated circuit and interconnect between the partitions are "laid out" (i.e. placed within the confines of the desired integrated circuit dimensions) and the wiring between the partitions is routed through the wiring layers. Once the layout is completed, an extraction of the capacitance for the interconnect can be performed, and a final timing analysis including the interconnect delay and delays for the cells is performed to verify that the integrated circuit meets the design goals for the integrated circuit.
A typical cell library includes multiple cells implementing the same basic logical function (e.g. AND, OR, NAND, NOR, etc.) or complex logical function. The multiple cells correspond to different circuits. The number and configuration of the transistors may vary between the circuits corresponding to each of the cells. Alternatively, the "drive strength" may be varied between different circuits having the same number and configuration of transistors. The drive strength is a measure of the circuits ability to charge/discharge a largely capacitive load (e.g. the input pins of other cells plus the wiring there between). A high drive strength indicates the ability to charge/discharge a large load quickly, while a low drive strength indicates a longer time period for charging/discharging a large load. The drive strength may be characterized by an output resistance for the cell. Typically, a circuit having a higher drive strength occupies more area than an equivalent circuit having a lower drive strength (the transistors are made larger to increase the drive strength, for example).
The synthesis tool uses the multiple cells corresponding to a given logical function to realize the RTL description within the area, timing, and other constraints for the integrated circuit. If the timing of a particular logic path is not close to the maximum desired clock cycle time, then cells having a lower drive strength may be selected for that path to minimize the area occupied by those circuits. Additionally, different combinations of cells may form the same overall logical functions, and the different combinations may have different timing and area characteristics. The synthesis tool tries different combinations of drive strengths and different combinations of cells to realize a given RTL description. If none of the selected combinations can realize the RTL description within the design constraints, the synthesis tool selects the combination which is closest to achieving the constraints. Generally speaking, a synthesis tool is a computer program which performs integrated circuit design synthesis. An exemplary synthesis tool is the Design Compiler family of tools available from Synopsys, Inc. of Mountainview, Calif.
Unfortunately, the time required to synthesize an RTL description given multiple drive strengths per logical function and/or multiple circuit types providing an equivalent function can be prohibitive. The time required is particularly prohibitive during the early synthesis attempts performed upon the RTL description. The RTL description provided during the early attempts to synthesize the integrated circuit may require significant optimization before an acceptable synthesis result can be achieved. Additionally, the functionality of the RTL description may need to be modified to achieve an acceptable synthesis result. These early synthesis attempts, then, provide an evaluation of the RTL description and the integrated circuit design itself. Therefore, it is desirable to be able to quickly synthesize an RTL description in order to evaluate the RTL.
In some cases, a library of cells corresponding to a set of circuits designed for a particular semiconductor fabrication process may not be available until after initiation of synthesis is desired. The design cycle (i.e. the time elapsing between defining the design goals of an integrated circuit and the fabrication of the integrated circuit) may be lengthened by the inability to evaluate the RTL description of the integrated circuit earlier in the design cycle.